# This file is part of linux driver the digital TV devices equipped with B2C2 FlexcopII(b)/III
# register descriptions
# see flexcop.c for copyright information.


$copyright = <<EOL;
/* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
 *
 * register descriptions
 *
 * see flexcop.c for copyright information.
 */
EOL

$regs = [

# DMA1 0x000 to 0x00c
# DMA2 0x010 to 0x01c
	dma_0x0 => [
		dma_0start        => 1,		# set=> data will be delivered to dma1_address0
        dma_0No_update    => 1,		# set=> dma1_cur_address will be updated, unset: no update
        dma_address0      => 30,	# physical/virtual host memory address0 DMA
	],

	dma_0x4_remap => [
		DMA_maxpackets    => 8,		# (remapped) PCI DMA1 Packet Count Interrupt. This variable
									# is able to be read and written while bit(1) of register
									# 0x00c (remap_enable) is set. This variable represents
									# the number of packets that will be transmitted to the PCI
									# host using PCI DMA1 before an interrupt to the PCI is
									# asserted. This functionality may be enabled using bit(20)
									# of register 0x208. N=0 disables the IRQ.
		dma_addr_size     => 24,	# size of memory buffer in DWORDs (bytesize / 4) for DMA
	],

	dma_0x4_read => [
		dma1timer         => 7,		# reading PCI DMA1 timer ... when remap_enable is 0
		unused            => 1,
		dma_addr_size     => 24,	# DMA addr
	],

	dma_0x4_write => [
		unused            => 1,
		dmatimer          => 7,		# writing PCI DMA1 timer ... when remap_enable is 0
		dma_addr_size     => 24,
	],

	dma_0x8 => [
		unused            =>  2,
		dma_cur_addr      => 30,	# current physical host memory address pointer for DMA
	],

	dma_0xc => [
		dma_1start        =>  1,	# set=> data will be delivered to dma_address1, when dma_address0 is full
		remap_enable      =>  1,	# remap enable for 0x0x4(7=>0)
		dma_address1      => 30,	# Physical/virtual address 1 on DMA
	],

# Two-wire Serial Master and Clock 0x100-0x110
	tw_sm_c_100 => [
#		slave_transmitter =>  1,	# ???
		chipaddr          =>  7,	# two-line serial address of the target slave
		reserved1         =>  1,
		baseaddr          =>  8,	# address of the location of the read/write operation
		data1_reg         =>  8,	# first byte in two-line serial read/write operation
		working_start     =>  1,	# when doing a write operation this indicator is 0 when ready
									# set to 1 when doing a write operation
		twoWS_rw          =>  1,	# read/write indicator (1 = read, 0 write)
		total_bytes       =>  2,	# number of data bytes in each two-line serial transaction (0 = 1 byte, 11 = 4byte)
		twoWS_port_reg    =>  2,	# port selection=> 01 - Front End/Demod, 10 - EEPROM, 11 - Tuner
		no_base_addr_ack_error => 1,	# writing=> write-req=> frame is produced w/o baseaddr, read-req=> read-cycles w/o
										# preceding address assignment write frame
										# ACK_ERROR = 1 when no ACK from slave in the last transaction
		st_done           =>  1,	# indicator for transaction is done
	],

	tw_sm_c_104 => [
		data2_reg         =>  8,	# 2nd data byte
		data3_reg         =>  8,	# 3rd data byte
		data4_reg         =>  8,	# 4th data byte
		exlicit_stops     =>  1,	# when set, transactions are produced w/o trailing STOP flag, then send isolated STOP flags
		force_stop        =>  1,	# isolated stop flag
		unused            =>  6,
	],

# Clock. The register allows the FCIII to convert an incoming Master clock
# (MCLK) signal into a lower frequency clock through the use of a LowCounter
# (TLO) and a High- Counter (THI). The time counts for THI and TLO are
# measured in MCLK, each count represents 4 MCLK input clock cycles.
#
# The default output for port #1 is set for Front End Demod communication. (0x108)
# The default output for port #2 is set for EEPROM communication.          (0x10c)
# The default output for port #3 is set for Tuner communication.           (0x110)

	tw_sm_c_108 => [
		thi1              =>  6,	# Thi for port #1 (def=> 100110b, 38)
		reserved1         =>  2,
		tlo1              =>  5,	# Tlo for port #1 (def=> 11100b, 28)
		reserved2         => 19,
	],

	tw_sm_c_10c => [
		thi1              =>  6,	# Thi for port #2 (def=> 111001b, 57)
		reserved1         =>  2,
		tlo1              =>  5,	# Tlo for port #2 (def=> 11100b, 28)
		reserved2         => 19,
	],

	tw_sm_c_110 => [
		thi1              =>  6,	# Thi for port #3 (def=> 111001b, 57)
		reserved1         =>  2,
		tlo1              =>  5,	# Tlo for port #3 (def=> 11100b, 28)
		reserved2         => 19,
	],

# LNB Switch Frequency 0x200
# Clock that creates the LNB switch tone. The default is set to have a fixed
# low output (not oscillating) to the LNB_CTL line.

	lnb_switch_freq_200 => [
		LNB_CTLHighCount_sig => 15,	# It is the number of pre-scaled clock cycles that will be low.
		LNB_CTLLowCount_sig  => 15,	# For example, to obtain a 22KHz output given a 45 Mhz Master
									# Clock signal (MCLK), set PreScalar=01 and LowCounter value to 0x1ff.
		LNB_CTLPrescaler_sig =>  2,	# pre-scaler divides MCLK=> 00 (no division), 01 by 2, 10 by 4, 11 by 12
	],

# ACPI, Peripheral Reset, LNB Polarity
# ACPI power conservation mode, LNB polarity selection (low or high voltage),
# and peripheral reset.
	misc_204 => [
		ACPI1_sig         =>  1,	# turn of the power of tuner and LNB, not implemented in FCIII
		ACPI3_sig         =>  1,	# turn of power of the complete satelite receiver board (except FCIII)
		LNB_L_H_sig       =>  1,	# low or high voltage for LNB. (0 = low, 1 = high)
		Per_reset_sig     =>  1,	# misc. init reset (default=> 1), to reset set to low and back to high
		reserved          => 20,
		Rev_N_sig_revision_hi =>  4,	# 0xc in case of FCIII
		Rev_N_sig_reserved1 =>  2,
		Rev_N_sig_caps    =>  1,	# if 1, Flexcop has 32 PID- and MAC-filters and is capable of IP multicast
		Rev_N_sig_reserved2 =>  1,
	],

# Control and Status 0x208 to 0x21c
# Gross enable and disable control
	ctrl_208 => [
		Stream1_filter_sig =>  1,	# Stream1 PID filtering
		Stream2_filter_sig =>  1,	# Stream2 PID filtering
		PCR_filter_sig    =>  1,	# PCR PID filter
		PMT_filter_sig    =>  1,	# PMT PID filter

		EMM_filter_sig    =>  1,	# EMM PID filter
		ECM_filter_sig    =>  1,	# ECM PID filter
		Null_filter_sig   =>  1,	# Filters null packets, PID=0x1fff.
		Mask_filter_sig   =>  1,	# mask PID filter

		WAN_Enable_sig    =>  1,	# WAN output line through V8 memory space is activated.
		WAN_CA_Enable_sig =>  1,	# not in FCIII
		CA_Enable_sig     =>  1,	# not in FCIII
		SMC_Enable_sig    =>  1,	# CI stream data (CAI) goes directly to the smart card intf (opposed IBI 0x600 or SC-cmd buf).

		Per_CA_Enable_sig =>  1,	# not in FCIII
		Multi2_Enable_sig =>  1,	# ?
		MAC_filter_Mode_sig =>  1,	# (MAC_filter_enable) Globally enables MAC filters for Net PID filteres.
		Rcv_Data_sig      =>  1,	# PID filtering module enable. When this bit is a one, the PID filter will
									# examine and process packets according to all other (individual) PID
									# filtering controls. If it is at zero, no packet processing of any kind will
									# take place. All data from the tuner will be thrown away.

		DMA1_IRQ_Enable_sig =>  1,	# When set, a DWORD counter is enabled on PCI DMA1 that asserts the PCI
									# interrupt after the specified count for filling the buffer.
		DMA1_Timer_Enable_sig =>  1,# When set, a timer is enabled on PCI DMA1 that asserts the PCI interrupt
									# after a specified amount of time.
		DMA2_IRQ_Enable_sig =>  1,	# same as DMA1_IRQ_Enable_sig but for DMA2
		DMA2_Timer_Enable_sig =>  1,	# same as DMA1_Timer_Enable_sig but for DMA2

		DMA1_Size_IRQ_Enable_sig =>  1,	# When set, a packet count detector is enabled on PCI DMA1 that asserts the PCI interrupt.
		DMA2_Size_IRQ_Enable_sig =>  1,	# When set, a packet	count detector is enabled on PCI DMA2 that asserts the PCI interrupt.
		Mailbox_from_V8_Enable_sig =>  1,	# When set, writes to the mailbox register produce an interrupt to the
											# PCI host to indicate that mailbox data is available.

		unused            => 9,
	],

# General status. When a PCI interrupt occurs, this register is read to
# discover the reason for the interrupt.
	irq_20c => [
		DMA1_IRQ_Status   =>  1,	# When set(1) the DMA1 counter had generated an IRQ. Read Only.
		DMA1_Timer_Status =>  1,	# When set(1) the DMA1 timer had generated an IRQ. Read Only.
		DMA2_IRQ_Status   =>  1,	# When set(1) the DMA2 counter had generated an IRQ. Read Only.
		DMA2_Timer_Status =>  1,	# When set(1) the DMA2 timer had generated an IRQ. Read Only.
		DMA1_Size_IRQ_Status =>  1,	# (Read only). This register is read after an interrupt to
		DMA2_Size_IRQ_Status =>  1,	# find out why we had an IRQ. Reading this register will clear this bit. Packet count
		Mailbox_from_V8_Status_sig => 1,	# Same as above. Reading this register will clear this bit.
		Data_receiver_error =>  1,	# 1 indicate an error in the receiver Front End (Tuner module)
		Continuity_error_flag =>  1,	# 1 indicates a continuity error in the TS stream.
		LLC_SNAP_FLAG_set =>  1,	# 1 indicates that the LCC_SNAP_FLAG was set.
		Transport_Error   =>  1,	#  When set indicates that an unexpected packet was received.
		reserved          => 21,
	],


# Software reset register
	sw_reset_210 => [
		reset_block_000   =>  1,	# Enabled when Block_reset_enable = 0xB2 and 0x208 bits 15=>8 = 0x00.
		reset_block_100   =>  1,	# Each bit location represents a 0x100 block of registers. Writing
		reset_block_200   =>  1,	# a one in a bit location resets that block of registers and the logic
		reset_block_300   =>  1,	# that it controls.
		reset_block_400   =>  1,
		reset_block_500   =>  1,
		reset_block_600   =>  1,
		reset_block_700   =>  1,
		Block_reset_enable =>  8,	# This variable is set to 0xB2 when the register is written.
		Special_controls  => 16,	# Asserts Reset_V8 => 0xC258, Turns on pci encryption => 0xC25A,
									# Turns off pci encryption => 0xC259 Note=> pci_encryption default
									# at power-up is ON.
	],

	misc_214 => [
		vuart_oe_sig      =>  1,	# When clear, the V8 processor has sole control of the serial UART
									# (RS-232 Smart Card interface). When set, the IBI interface
									# defined by register 0x600 controls the serial UART.
		v2WS_oe_sig       =>  1,	# When clear, the V8 processor has direct control of the Two-line
									# Serial Master EEPROM target. When set, the Two-line Serial Master
									# EEPROM target interface is controlled by IBI register 0x100.
		halt_V8_sig       =>  1,	# When set, contiguous wait states are applied to the V8-space
									# bus masters. Once this signal is cleared, normal V8-space
									# operations resume.
		section_pkg_enable_sig =>  1,	# When set, this signal enables the front end translation circuitry
										# to process section packed transport streams.
		s2p_sel_sig       =>  1,	# Serial to parallel conversion. When set, polarized transport data
									# within the FlexCop3 front end circuitry is converted from a serial
									# stream into parallel data before downstream processing otherwise
									# interprets the data.
		unused1           =>  3,
		polarity_PS_CLK_sig=>  1,	# This signal is used to invert the input polarity of the tranport
									# stream CLOCK signal before any processing occurs on the transport
									# stream within FlexCop3.
		polarity_PS_VALID_sig=>  1,	# This signal is used to invert the input polarity of the tranport
									# stream VALID signal before any processing occurs on the transport
									# stream within FlexCop3.
		polarity_PS_SYNC_sig=>  1,	# This signal is used to invert the input polarity of the tranport
									# stream SYNC signal before any processing occurs on the transport
									# stream within FlexCop3.
		polarity_PS_ERR_sig=>  1,	# This signal is used to invert the input polarity of the tranport
									# stream ERROR signal before any processing occurs on the transport
									# stream within FlexCop3.
		unused2           => 20,
	],

# Mailbox from V8 to host
	mbox_v8_to_host_218 => [
		Mailbox_from_V8   => 32,	# When this register is written by either the V8 processor or by an
									# end host, an interrupt is generated to the PCI host to indicate
									# that mailbox data is available. Reading register 20c will clear
									# the IRQ.
	],

# Mailbox from host to v8 Mailbox_to_V8
# Mailbox_to_V8 mailbox storage register
# used to send messages from PCI to V8. Writing to this register will send an
# IRQ to the V8. Then it can read the data from here. Reading this register
# will clear the IRQ. If the V8 is halted and bit 31 of this register is set,
# then this register is used instead as a direct interface to access the
# V8space memory.

	mbox_host_to_v8_21c => [
		sysramaccess_data =>  8,	# Data byte written or read from the specified address in V8 SysRAM.
		sysramaccess_addr => 15,	# 15 bit address used to access V8 Sys-RAM.
		unused            =>  7,
		sysramaccess_write=>  1,	# Write flag used to latch data into the V8 SysRAM.
		sysramaccess_busmuster=>  1,	# Setting this bit when the V8 is halted at 0x214 Bit(2) allows
										# this IBI register interface to directly drive the V8-space memory.
	],

# PIDs, Translation Bit, SMC Filter Select 0x300 to 0x31c
	pid_filter_300 => [
		Stream1_PID       => 13,	# Primary use is receiving Net data, so these 13 bits normally
									# hold the PID value for the desired network stream.
		Stream1_trans     =>  1,	# When set, Net translation will take place for Net data ferried in TS packets.
		MAC_Multicast_filter =>  1,	# When clear, multicast MAC filtering is not allowed for Stream1 and PID_n filters.
		debug_flag_pid_saved =>  1,
		Stream2_PID       => 13,	# 13 bits for Stream 2 PID filter value. General use.
		Stream2_trans     =>  1,	# When set Tables/CAI translation will take place for the data ferried in
									# Stream2_PID TS packets.
		debug_flag_write_status00 =>  1,
		debug_fifo_problem =>  1,
	],

	pid_filter_304 => [
		PCR_PID           => 13,	# PCR stream PID filter value. Primary use is Program Clock Reference stream filtering.
		PCR_trans         =>  1,	# When set, Tables/CAI translation will take place for these packets.
		debug_overrun3    =>  1,
		debug_overrun2    =>  1,
		PMT_PID           => 13,	# stream PID filter value. Primary use is Program Management Table segment filtering.
		PMT_trans         =>  1,	# When set, Tables/CAI translation will take place for these packets.
		reserved          =>  2,
	],

	pid_filter_308 => [
		EMM_PID           => 13,	# EMM PID filter value. Primary use is Entitlement Management Messaging for
									# conditional access-related data.
		EMM_trans         =>  1,	# When set, Tables/CAI translation will take place for these packets.
		EMM_filter_4      =>  1,	# When set will pass only EMM data possessing the same ID code as the
									# first four bytes (32 bits) of the end-user s 6-byte Smart Card ID number Select
		EMM_filter_6      =>  1,	# When set will pass only EMM data possessing the same 6-byte code as the end-users
									# complete 6-byte Smart Card ID number.
		ECM_PID           => 13,	# ECM PID filter value. Primary use is Entitlement Control Messaging for conditional
									# access-related data.
		ECM_trans         =>  1,	# When set, Tables/CAI translation will take place for these packets.
		reserved          =>  2,
	],

	pid_filter_30c_ext_ind_0_7 => [
		Group_PID         => 13,	# PID value for group filtering.
		Group_trans       =>  1,	# When set, Tables/CAI translation will take place for these packets.
		unused1           =>  2,
		Group_mask        => 13,	# Mask value used in logical "and" equation that defines group filtering
		unused2           =>  3,
	],

	pid_filter_30c_ext_ind_1 => [
		net_master_read   => 17,
		unused            => 15,
	],

	pid_filter_30c_ext_ind_2 => [
		net_master_write  => 17,
		unused            => 15,
	],

	pid_filter_30c_ext_ind_3 => [
		next_net_master_write =>17,
		unused            =>15,
	],

	pid_filter_30c_ext_ind_4 => [
		unused1           =>  1,
		state_write       => 10,
		reserved1         =>  6,	# default=> 000100
		stack_read        => 10,
		reserved2         =>  5,	# default=> 00100
	],

	pid_filter_30c_ext_ind_5 => [
		stack_cnt         => 10,
		unused            => 22,
	],

	pid_filter_30c_ext_ind_6 => [
		pid_fsm_save_reg0 =>  2,
		pid_fsm_save_reg1 =>  2,
		pid_fsm_save_reg2 =>  2,
		pid_fsm_save_reg3 =>  2,
		pid_fsm_save_reg4 =>  2,
		pid_fsm_save_reg300 =>  2,
		write_status1 =>  2,
		write_status4 =>  2,
		data_size_reg => 12,
		unused        =>  4,
	],

	index_reg_310 => [
		index_reg         =>  5,	# (Index pointer) Points at an internal PIDn register. A binary code
									# representing one of 32 internal PIDn registers as well as its
									# corresponding internal MAC_lown register.
		extra_index_reg   =>  3,	# This vector is used to select between sets of debug signals routed to register 0x30c.
		AB_select         =>  1,	# Used in conjunction with 0x31c. read/write to the MAC_highA or MAC_highB register
						 			# 0=MAC_highB register, 1=MAC_highA
		pass_alltables    =>  1,	# 1=Net packets are not filtered against the Network Table ID found in register 0x400.
									# All types of networks (DVB, ATSC, ISDB) are passed.
		unused            => 22,
	],

	pid_n_reg_314 => [
		PID               => 13,	# PID value
		PID_trans         =>  1,	# translation will take place for packets filtered
		PID_enable_bit    =>  1,	# When set this PID filter is enabled
		reserved          => 17,
	],

	mac_low_reg_318 => [
		A4_byte           =>  8,
		A5_byte           =>  8,
		A6_byte           =>  8,
		Enable_bit        =>  1,	# enabled (1) or disabled (0)
		HighAB_bit        =>  1,	# use MAC_highA (1) or MAC_highB (0) as MSB
		reserved          =>  6,
	],

	mac_high_reg_31c => [
		A1_byte           =>  8,
		A2_byte           =>  8,
		A3_byte           =>  8,
		reserved          =>  8,
	],

# Table, SMCID,MACDestination Filters 0x400 to 0x41c
	data_tag_400 => [
		reserved          => 16,
		data_Tag_ID       => 16,
	],

	card_id_408 => [
		Card_IDbyte6      =>  8,
		Card_IDbyte5      =>  8,
		Card_IDbyte4      =>  8,
		Card_IDbyte3      =>  8,
	],

	card_id_40c => [
		Card_IDbyte2      =>  8,
		Card_IDbyte1      =>  8,
	],

	# holding the unique mac address of the receiver which houses the FlexCopIII
	mac_address_418 => [
		MAC1              =>  8,
		MAC2              =>  8,
		MAC3              =>  8,
		MAC6              =>  8,
	],

	mac_address_41c => [
		MAC7              =>  8,
		MAC8              =>  8,
		reserved          =>  16,
	],

	ci_600 => [
		transmitter_data_byte => 8,
		ReceiveDataReady  =>  1,
		ReceiveByteFrameError => 1,
		txbuffempty       =>  1,
		reserved          => 21,
	],

	pi_604 => [
		pi_d              =>  8,
		pi_ha             => 20,
		pi_rw             =>  1,
		pi_component_reg  =>  3,
	],

	pi_608 => [
		serialReset       =>  1,
		oncecycle_read    =>  1,
		Timer_Read_req    =>  1,
		Timer_Load_req    =>  1,
		timer_data        =>  7,
		unused            =>  1,	# ??? not mentioned in data book
		Timer_addr        =>  5,
		reserved          =>  3,
		pcmcia_a_mod_pwr_n =>  1,
		pcmcia_b_mod_pwr_n =>  1,
		config_Done_stat  =>  1,
		config_Init_stat  =>  1,
		config_Prog_n     =>  1,
		config_wr_n       =>  1,
		config_cs_n       =>  1,
		config_cclk       =>  1,
		pi_CiMax_IRQ_n    =>  1,
		pi_timeout_status =>  1,
		pi_wait_n         =>  1,
		pi_busy_n         =>  1,
	],

	dvb_reg_60c => [
		PID               => 13,
		key_enable        =>  1,
#define fc_key_code_default 0x1
#define fc_key_code_even    0x2
#define fc_key_code_odd     0x3
		key_code          =>  2,
		key_array_col     =>  3,
		key_array_row     =>  5,
		dvb_en            =>  1,	# 0=TS bypasses the Descrambler
		rw_flag           =>  1,
		reserved          =>  6,
	],

# SRAM and Output Destination 0x700 to 0x714
	sram_ctrl_reg_700 => [
		sram_addr         => 15,
		sram_rw           =>  1,	# 0=write, 1=read
		sram_data         =>  8,
		sc_xfer_bit       =>  1,
		reserved1         =>  3,
		oe_pin_reg        =>  1,
		ce_pin_reg        =>  1,
		reserved2         =>  1,
		start_sram_ibi    =>  1,
	],

	net_buf_reg_704 => [
		net_addr_read     => 16,
		net_addr_write    => 16,
	],

	cai_buf_reg_708 => [
		cai_read          => 11,
		reserved1         =>  5,
		cai_write         => 11,
		reserved2         =>  6,
		cai_cnt           =>  4,
	],

	cao_buf_reg_70c => [
		cao_read          => 11,
		reserved1         =>  5,
		cap_write         => 11,
		reserved2         =>  6,
		cao_cnt           =>  4,
	],

	media_buf_reg_710 => [
		media_read        => 11,
		reserved1         =>  5,
		media_write       => 11,
		reserved2         =>  6,
		media_cnt         =>  4,
	],

	sram_dest_reg_714 => [
		NET_Dest          =>  2,
		CAI_Dest          =>  2,
		CAO_Dest          =>  2,
		MEDIA_Dest        =>  2,
		net_ovflow_error  =>  1,
		media_ovflow_error =>  1,
		cai_ovflow_error  =>  1,
		cao_ovflow_error  =>  1,
		ctrl_usb_wan      =>  1,
		ctrl_sramdma      =>  1,
		ctrl_maximumfill  =>  1,
		reserved          => 17,
	],

	net_buf_reg_718 => [
		net_cnt           => 12,
		reserved1         =>  4,
		net_addr_read     =>  1,
		reserved2         =>  3,
		net_addr_write    =>  1,
		reserved3         => 11,
	],

	wan_ctrl_reg_71c => [
		wan_speed_sig     =>  2,
		reserved1         =>  6,
		wan_wait_state    =>  8,
		sram_chip         =>  2,
		sram_memmap       =>  2,
		reserved2         =>  4,
		wan_pkt_frame     =>  4,
		reserved3         =>  4,
	],
];

1;
