/*
 * i8259.i86  -  Definitions for accessing the 8259 interrupt controller
 *
 * Copyright (C) 2003-2007 Gero Kuhlmann   <gero@gkminix.han.de>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * $Id: i8259.i86,v 1.7 2007/01/06 18:31:09 gkminix Exp $
 */

#ifndef SYSTEM_I8259_I86
#define SYSTEM_I8259_I86


/*
 * This file can only get included into assembler source files
 */
#if !defined(_ASSEMBLY_) || !defined(_TARGET_)
# error This file can only get included into assembler source files
#endif



/*
 * I/O addresses used by PICs in a typical PC:
 */
#define MASTER_CMD		0x20	/* master PIC command port */
#define MASTER_IMR		0x21	/* master PIC interrupt mask register */
#define SLAVE_CMD		0xA0	/* slave PIC command port */
#define SLAVE_IMR		0xA1	/* slave PIC interrupt mask register */



/*
 * Command codes for i8259A:
 */
#define CMD_NS_EOI		0x20	/* non-specific EOI command */
#define CMD_S_EOI		0x60	/* specific EOI command */
#define CMD_READ_IRR		0x0A	/* read IR register */
#define CMD_READ_ISR		0x0B	/* read IS register */
#define CMD_SET_SMM		0x68	/* set special-mask mode */
#define CMD_RST_SMM		0x48	/* reset special-mask mode */



/*
 * Definitions used for handling the redirected slave interrupt on AT and
 * higher systems:
 */
#define SLAVE_IRQ_MASK		0x04	/* IRQ mask for slave PIC on master */
#define SLAVE_IRQ_NUM		2	/* IRQ number for slave PIC on master */
#define SLAVE_IRQ_REDIR		9	/* IRQ number for redirected int 2 */



/*
 * Interrupt vector ranges with some special meaning:
 *
 * Hardware interrupts. Note that some master PIC hardware interrupts may
 * also be generated by CPU error conditions.
 */
#define MIN_MASTER_HWINT	0x08	/* first interrupt vector on master */
#define MAX_MASTER_HWINT	0x0F	/* last interrupt vector on master */

#define MIN_SLAVE_HWINT		0x70	/* first interrupt vector on slave */
#define MAX_SLAVE_HWINT		0x77	/* last interrupt vector on slave */

#define PIC_IRQ_NUM		8	/* number of IRQs per PIC */



/*
 * Define minimum and maximum hardware interrupt line numbers. These are
 * used for a rough check if a hardware interrupt is correct. It has to
 * be within the specified range. These are IRQ numbers, not vector numbers!
 */
#define HWIRQ_MIN		3
#define HWIRQ_MAX		14



/*
 * Define hardware interrupt vectors, which are usually assigned some
 * special meaning in PC/AT compatible systems:
 */
#define HWINT_TIMER		0x08	/* hardware timer interrupt */
#define HWINT_KBD		0x09	/* keyboard data ready interrupt */
#define HWINT_LPT2_XT		0x0A	/* LPT2 interrupt on old PC/XT */
#define HWINT_SLAVE		0x0A	/* slave PIC interrupt on PC/AT */
#define HWINT_COM2		0x0B	/* COM2 interrupt */
#define HWINT_COM1		0x0C	/* COM1 interrupt */
#define HWINT_LPT2_AT		0x0D	/* LPT2 interrupt on PC/AT */
#define HWINT_HD_XT		0x0D	/* hard disk interrupt on old PC/XT */
#define HWINT_DISKETTE		0x0E	/* diskette driver interrupt */
#define HWINT_LPT1		0x0F	/* LPT1 interrupt */

#define HWINT_CLOCK		0x70	/* CMOS clock interrupt */
#define HWINT_IRQ9		0x71	/* IRQ 2 hardware interrupt */
#define HWINT_MOUSE_PS2		0x74	/* PS/2 mouse interrupt */
#define HWINT_MATHERR		0x75	/* math coprocessor error */
#define HWINT_HD_AT		0x76	/* hard disk interrupt on PC/AT */



/*
 * Size of processor interrupt table
 */
#define IDT_NUM		256


#endif

