/*
 *  linux/drivers/char/serial_psionw.h
 */

/* Common with AMBA */
#define AMBA_ISR_PASS_LIMIT	256
#define AMBA_UARTIIR		0x1C	/* Same as Psion UARTINTR (Read only) */
#define AMBA_UARTDR		0x00	/* Data read or written from the interface. */
#define AMBA_UARTRSR		0x04	/* Receive status register (Read only). */
#define AMBA_UARTFR_TXFF	0x20	/* Same as Psion UTXFF */
#define AMBA_UARTFR_RXFE	0x10	/* Same as Psion URXFE */
#define AMBA_UARTFR_BUSY	0x08	/* Same as Psion UBUSY */
#define AMBA_UARTFR_DCD		0x04	/* Same as Psion DCD */
#define AMBA_UARTFR_DSR		0x02	/* Same as Psion DSR */
#define AMBA_UARTFR_CTS		0x01	/* Same as Psion CTS */
#define AMBA_UARTFR_TMSK	(AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY)

/* Psion specific port base addresses */
#define PSIONW_UART0_BASE	(0x0600)
#define PSIONW_UART1_BASE	(0x0700)
#define PSIONW_UART0_V_BASE	(PSIONW_BASE + PSIONW_UART0_BASE)
#define PSIONW_UART1_V_BASE	(PSIONW_BASE + PSIONW_UART1_BASE)

/* Offsets from the base address for each port */
#define PSIONW_UARTDR		(0x00)	/* Data register */
#define PSIONW_UARTFCR		(0x04)	/* Frame control register */
#define PSIONW_UARTLCR		(0x08)	/* Line control register, UBRCR */
#define PSIONW_UARTCON		(0x0c)	/* Port control register */
#define PSIONW_UARTFR		(0x10)	/* Flag register (Read only) UARTFLG */
#define PSIONW_UARTINT		(0x14)	/* Second level interrupt register */
#define PSIONW_UARTINTM		(0x18)	/* Interrupt mask register */
#define PSIONW_UARTINTR		(0x1c)	/* Interrupt raw status register (Read only) */
#define PSIONW_UARTTR1		(0x20)	/* Test register */
#define PSIONW_UARTTR2		(0x24)	/* Test register */
#define PSIONW_UARTTR3		(0x28)	/* Test register */

#define PSIONW_UART_RXINT	(1 << 0)	/* Rx interrupt */
#define PSIONW_UART_TXINT	(1 << 1)	/* Tx interrupt */
#define PSIONW_UART_MSINT	(1 << 2)	/* Modem status interrupt */

#define PSIONW_UART_BAUD_MASK	((1 << 16) - 1)
#define PSIONW_UARTTR3_IRUBLOCK	(1 << 1)	/* Unblock irda rx */

#define PSIONW_UARTCR_UARTEN	(1 << 0)	/* Uart enable */
#define PSIONW_UARTCR_SIREN	(1 << 1)	/* SiR disable, clear to enable IrDA */
#define PSIONW_UARTCR_IRTXM	(1 << 2)	/* IrDA Tx mode bit, set for power savings */

#define PSIONW_UARTRSR_FE	(1 << 8)	/* Frame error */
#define PSIONW_UARTRSR_PE	(1 << 9)	/* Parity error */
#define PSIONW_UARTRSR_OE	(1 << 10)	/* Overrun error */

#define PSIONW_UARTFCR_BREAK		(1 << 0)
#define PSIONW_UARTFCR_PRTEN		(1 << 1)
#define PSIONW_UARTFCR_EVENPRT		(1 << 2)
#define PSIONW_UARTFCR_XSTOP		(1 << 3)
#define PSIONW_UARTFCR_UFIFOEN		(1 << 4)
#define PSIONW_UARTFCR_WLEN_5		(0 << 5)
#define PSIONW_UARTFCR_WLEN_6		(1 << 5)
#define PSIONW_UARTFCR_WLEN_7		(2 << 5)
#define PSIONW_UARTFCR_WLEN_8		(3 << 5)
#define PSIONW_UARTFCR_WRDLEN_MASK	(3 << 5)

#define UART_PORT_SIZE		64

#define PSIONW_UARTFR_MODEM_ANY	(AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS)

/* No modem break in Psion */
#define PSIONW_UARTRSR_ANY	(PSIONW_UARTRSR_OE|PSIONW_UARTRSR_PE|PSIONW_UARTRSR_FE)

#define UART_GET_INT_MASK(p)	readb((p)->membase + PSIONW_UARTINTM)
#define UART_PUT_INT_MASK(p,c)	writeb((c), (p)->membase + PSIONW_UARTINTM)
#define UART_CLEAR_INT(p,c)	writeb((c), (p)->membase + PSIONW_UARTINT)
#define UART_GET_INT_STATUS(p)	readb((p)->membase + PSIONW_UARTINTR)

#define UART_GET_FR(p)		readb((p)->membase + PSIONW_UARTFR)

#define UART_GET_CR(p)		readb((p)->membase + PSIONW_UARTCON)
#define UART_PUT_CR(p,c)	writeb((c), (p)->membase + PSIONW_UARTCON)

#define UART_PUT_CHAR(p, c)	writeb((c), (p)->membase + AMBA_UARTDR)

/* Must be readl for error bits */
#define UART_GET_CHAR(p)	readl((p)->membase + AMBA_UARTDR)
#define UART_RX_DATA(s)		(((s) & AMBA_UARTFR_RXFE) == 0)
#define UART_TX_READY(s)	(((s) & AMBA_UARTFR_TXFF) == 0)
#define UART_TX_EMPTY(p)	((UART_GET_FR(p) & AMBA_UARTFR_TMSK) == 0)
#define UART_GET_RSR(p)		readb((p)->membase + AMBA_UARTRSR)

#define UART_GET_FCR(p)		readb((p)->membase + PSIONW_UARTFCR)
#define UART_PUT_FCR(p,c)	writeb((c), (p)->membase + PSIONW_UARTFCR)

#define UART_GET_LCR(p)		readl((p)->membase + PSIONW_UARTLCR)
#define UART_PUT_LCR(p,c)	writel((c), (p)->membase + PSIONW_UARTLCR)
